EDA 课程设计拔河游戏机 ？
一、总体设计思想
电子拔河游戏机是一种能容纳甲乙双方参赛游戏电路。由一排发光二极管表示拔河的“电子绳”。由甲乙双方通过按纽开关使发光二极管向一方的终点延伸，当延伸到某方的最后一个发光二极管时，?则该方获胜，连续比赛多局以定胜负。
1.基本原理
本电路要求使用9个发光二极管，开机后只有中间一个发亮，此即拔河的中心点。游戏双方各持一个按钮，迅速地、不断地按动，产生脉冲，谁按得快，亮点就向谁的方向移动，每按一次，亮点移动一次。亮点移到任一方终端二极管时，这一方就获胜，此时双方按钮均无作用，输出保持，只有复位后才使亮点恢复到中心。最后用数码管显示获胜者的盘数。
由设计内容可知，首先需要一个十进制的计数器，用于对双方按钮的次数计数，并通过译码器显示在数码管上。设计要求用50MHz的频率，而设计用到的是1K?Hz的频率，所以要设计一个程序进行分频。其次，显视控制部分设计要求在发光二极管上显示游戏状态，双方每按十次，亮点向先按十次移动一次，对脉冲进行计数，每十次移一位。需接入一个清零端?，用于复位。再次，运用VHDL程序语言进行各个模块的程序编写，控制电路的正常运行。最后，将以上程序组装起来，就可得到所需要的拔河游戏机
library?ieee;
use?ieee.std_logic_1164.all;
use?ieee.std_logic_unsigned.all;
entity?bahe?is?
port?(a,b,rst,clk:in?std_logic;
sg,led:out?std_logic_vector(8?downto?0);
bt:out?std_logic_vector(7?downto?0));
end?bahe;
----------------------------------
architecture?one?of?bahe?is
component?cnt10
port?(clk,rst,en:std_logic;
cout:out?std_logic;
cq:out?std_logic_vector(3?downto?0));
end?component;
component?scan?
port?(clk?:in?std_logic;
a1,?a2,a3,b1,b2,b3:in?std_logic_vector(3?downto?0);
sg:out?std_logic_vector(8?downto?0);
bt:?out?std_logic_vector(7?downto?0));
end?component;
component?lmov
port?(kl?,kr:in?std_logic_vector(3?downto?0)?;
led:out?std_logic_vector(8?downto?0);
en?:?out?std_logic;
rst:in?std_logic);
end?component;
signal?e,f,ca1,ca2,cb1,cb2:std_logic;
signal?cqa1,cqa2,cqa3,cqb1,cqb2,cqb3:std_logic_vector(3?downto?0);
begin
u1:?cnt10?port?map?(en=>e,rst=>rst,clk=>a,cout=>ca1,cq=>cqa1);
u2:?cnt10?port?map?(en=>e,rst=>rst,clk=>ca1,cout=>ca2,cq=>cqa2);
u3:?cnt10?port?map?(en=>e,rst=>rst,clk=>ca2,cq=>cqa3);
u4:?cnt10?port?map?(en=>e,rst=>rst,clk=>b,cout=>cb1,cq=>cqb1);
u5:?cnt10?port?map?(en=>e,rst=>rst,clk=>cb1,cout=>cb2,cq=>cqb2);
u6:?cnt10?port?map?(en=>e,rst=>rst,clk=>cb2,cq=>cqb3);
u7:?scan?port?map?(a1=>cqa1,a2=>cqa2,a3=>cqa3,b1=>cqb1,
b2=>cqb2,b3=>cqb3,clk=>clk,sg=>sg,bt=>bt);
u8:lmov?port?map?(en=>e,kl=>cqa2,kr=>cqb2,rst=>rst,led=>led);
end?architecture?one;
library?ieee;
use?ieee.std_logic_1164.all;
use?ieee.std_logic_unsigned.all;?
entity?cnt10?is
port(clk,rst,en:std_logic;
cout:out?std_logic;
cq:out?std_logic_vector(3?downto?0));
end;
architecture?one?of?cnt10?is
begin
process(clk,rst,en)
variable?cqi:std_logic_vector(3?downto?0);
begin?
if?rst='1'?then?
cqi:=(others=>'0');
elsif?clk'event?and?clk='1'?then?
if?en='1'?then?
if?cqi<9?then?cqi:=cqi+1;
else?cqi?:=(others=>'0');
end?if?;
end?if;
end?if;
if?c?qi=9?then?cout<='0'?;
else?cout<='1';
end?if;
cq<=cqi;
end?process;
end;
library?ieee;
use?ieee.std_logic_1164.all;
use?ieee.std_logic_unsigned.all;
entity?scan?is?
port?(clk?:in?std_logic;
a1,a2,a3,b1,b2,b3:in?std_logic_vector(3?downto?0);
sg:out?std_logic_vector(8?downto?0);
bt:?out?std_logic_vector(7?downto?0));
end;
architecture?one?of?scan?is
signal?cnt4:std_logic_vector(2?downto?0);
signal?a:std_logic_vector(3?downto?0);
signal?clk1:std_logic;
begin?
p1:process(cnt4)
begin
case?cnt4?is
when?"000"=>bt<="10000000";a<=a1;
when?"001"=>bt<="01000000";a<=a2;
when?"010"=>bt<="00100000";a<=a3;
when?"011"=>bt<="00000100";a<=b1;
when?"100"=>bt<="00000010";a<=b2;
when?"101"=>bt<="00000001";a<=b3;
when?others=>bt<="00000000";
end?case?;
end?process?p1;
---------------------------------
p2:process?(clk)
variable?ct:integer?range?0?to?50000;
begin?
if?clk'event?and?clk='1'?then?--1000HZ?
if?ct<49999?then
ct:=ct+1;
clk1<='0';
else?
ct:=0;
clk1<='1';
end?if;
end?if;
end?process?p2;
process(clk1)
begin?
if?clk1'event?an?d?clk1='1'?then
if?cnt4<5?then
cnt4<=cnt4+1;
else?
cnt4<="000";
end?if;
end?if;
end?process;
------------------------------------
process?(a)
begin?
case?a?is?
when?"0000"=>sg<="100000000";
when?"0001"=>sg<="111110001";
when?"0010"=>sg<="001001000";
when?"0011"=>sg<="001100000";
when?"0100"=>sg<="000110010";
when?"0101"=>sg<="000100100";
when?"0110"=>sg<="000000100";
when?"0111"=>sg<="111110000";
when?"1000"=>sg<="000000000";
when?"1001"=>sg<="100011111";
when?"1010"=>sg<="000100100";
when?"1011"=>sg<="000011000";
when?"1100"=>sg<="010001100";
when?"1101"=>sg<="001001000";
when?"1110"=>sg<="001000000";
when?"1111"=>sg<="000011111";
when?others=>null;
end?case?;
end?process;
end;
library?ieee;
use?ieee.std_logic_1164.all;
use?ieee.std_logic_unsigned.all;
entity?lmov?is?
port?(kl?,kr:in?std_logic_vector(3?downto?0)?;
led:out?std_logic_vector(8?downto?0);
en?:?out?std_logic;
rst:in?std_logic);
end?;
architecture?one?of?lmov?is
begin?
process(rst,kl,kr)
begin?
if?rst='1'?then?led<="111101111";en<='1';
elsif?kl-kr=1?then?led<="111011111";en<='1';
elsif?kl-kr=2?then?led<="110111111";en<='1';
elsif?kl-kr=3?then?led<="101111111";en<='1';
elsif?kl-kr=4?then?led<="011111111";en<='0';
elsif?kr-kl=1?then?led<="111110111";en<='1';
elsif?kr-kl=2?then?led<="111111011";en<='1'?;
elsif?kr-kl=3?then?led<="111111101";en<='1';
elsif?kl-kr=4?then?led<="111111110";en<='0';
elsif?kr-kl=0?then?led<="111101111";en<='1';
else?null;
end?if;
end?process;
end;